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binaryTObcd
- Binary to BCD converter in VHDL.
Converte_integer_to_bcd
- VHDL code for INTEGER conversion (0-255) to BCD code for display
2
- BCD码七段译码器CC4511,用VHDL语言来描述CC4511。-BCD code seven-segment decoder CC4511, using VHDL language to describe the CC4511.
altera_de2_vhdl
- Tutorial of VHDL with Altera DE2 board: quartus II and DE2 board The target do the BCD sum of input data coded with the switches and display the result on 7 segment display
vhdlsample
- vhdl program for bcd conter to 7 segment display
division_imp4_v5
- Code VHDL for Newton Raphson BCD Division and Carry Save Multiplication in BCD
Sum_Rest_BCD
- VHDL Sum and Rest BCD
2to10
- 2 to 10 bcd under vhdl langage in maxplus2 good one
hw4
- Write VHDL codes to show, on two 7-segment LEDs, the binary coded decimal (BCD) equivalence of the binary representation of the state of eight switches. Use a function to perform the specified task. Assume that the 7-segment LEDs are turned on with l
8421BCD
- 8421bcd 编码 把十进制数字转换为8421bcd型二进制序列,例如11=00010001-8421bcd coded decimal numbers into 8421bcd the type of binary sequences, such as 11 = 00010001
summator
- 加法器是产生数的和的装置。常用作计算机算术逻辑部件,执行逻辑操作、移位与指令调用。在电子学中,加法器是一种数位电路,其可进行数字的加法计算。在现代的电脑中,加法器存在于算术逻辑单元之中。 加法器可以用来表示各种数值,如:BCD、加三码,主要的加法器是以二进制作运算。加法器可以用组合逻辑电路实现也可以用VHDL语言实现。-Adder is generated and the number of devices. Arithmetic logic unit is used as a computer
BCD_CNT
- vhdl十进制计数器。完成计数长度为0-999的BCD码加法计数器,输出数据为三个宽度为4位的数据。-decimal counter vhdl
Counter24hour
- 用VHDL语言编写的一个二十四进制计数器,一个脉冲输入引脚,一个复位输入端,四个BCD码输出端。与我另外的八个模块是配配套的。-A 24 binary counter programmed with VHDL language.A pulse input, a reset input, four output BCD code. It is one of my total 9 modules that are used to design a digital clock.
Counter60sec
- VHDL语言编写的一个六十进制计数器(用于秒),一个脉冲输入引脚,一个复位引脚,8个BCD码输出引脚,一个进位输出引脚。与我的其它8个模块配套构成一个数字钟。 -A 60 binary counter(for second) programmed with VHDL language.A pulse input, a reset input, eight BCD code output. It is one of my total 9 modules that are used to de
db
- fulladder made by me I hope it works, the only thing I need from your database is the V74160.rar, the vhdl code for the 4 bit bcd counter with asynchronious reset.. please help me thank you
taximeter
- 设计一个出租车自动计费器,具有行车里程计费、等候时间计费、及起价三部分,用四位数码管显示总金额,最大值为99。99元; 行车里程单价1元/公里,等候时间单价0。5元/10分钟,起价3元(3公里起价)均能通过人工输入。 行车里程的计费电路将汽车行驶的里程数转换成与之成正比的脉冲数,然后由计数译码电路转换成收费金额,实验中以一个脉冲模拟汽车前进十米,则每100个脉冲表示1公里,然后用BCD码比例乘法器将里程脉冲乘以每公里单价的比例系数,比例系数可由开关预置。例如单价是1。0元/公里,则脉冲当
VHDL_BCD28
- vhdl code for BCD tranfer to 8 (LED light)
counterms
- verilog语言写的可置数的倒计时计数器,共四位bcd码,分别为分钟两位和秒两位。波形完美无毛刺.开发环境没找到verilog只好写了vhdl-verilog based counter for minutes and seconds
DECODER7
- 基于FPGA的BCD/七段译码器的设计,QuartusII编译通过,采用VHDL语言编写。-Based on FPGA BCD/these seven decoder design, QuartusII compile, USES the VHDL language.
convertor
- vhdl语言编写的,在QuartusII下,组合逻辑电路设计(4位二进制码到BCD码的转换器)的设计,经验证无错误-Four BCD binary switch